CD74HC175 具有复位功能的高速 CMOS 逻辑四路 D 类触发器
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.
Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1
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CD74HC175 |
| Technology Family |
AC |
| Rating |
Catalog |
CD74HC175 特性
- Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
- Positive Edge Pulse Triggering
- Complementary Outputs
- Buffered Inputs
- Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il
1µA at VOL, VOH
CD74HC175 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74HC175E |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD74HC175EE4 |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD74HC175M |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
| CD74HC175M96 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
| CD74HC175M96E4 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
| CD74HC175M96G4 |
ACTIVE |
-55 to 125 |
0.40 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
| CD74HC175ME4 |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
| CD74HC175MG4 |
ACTIVE |
-55 to 125 |
0.48 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
CD74HC175 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74HC175E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC175E |
CD74HC175E |
| CD74HC175EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC175EE4 |
CD74HC175EE4 |
| CD74HC175M |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175M |
CD74HC175M |
| CD74HC175M96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175M96 |
CD74HC175M96 |
| CD74HC175M96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175M96E4 |
CD74HC175M96E4 |
| CD74HC175M96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175M96G4 |
CD74HC175M96G4 |
| CD74HC175ME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175ME4 |
CD74HC175ME4 |
| CD74HC175MG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HC175MG4 |
CD74HC175MG4 |
CD74HC175 应用技术支持与电子电路设计开发资源下载
- CD74HC175 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
