This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA)\ input is low. Taking the output-enable (OEAB\ or OEBA)\ input low accesses the data on either port.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN74LVC2952A | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) | 2.0 to 3.6 |
| Input Level | LVTTL |
| Output Level | 8 |
| No. of Outputs | 0.01 |
| Static Current | TTL/CMOS |
| Technology Family | LVC |
| Rating | Catalog |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVC2952ADW | ACTIVE | 0 to 70 | 5.85 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVC2952ADWE4 | ACTIVE | 0 to 70 | 5.85 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVC2952ADWG4 | ACTIVE | 0 to 70 | 5.85 | 1ku | SOIC (DW) | 24 | 25 | TUBE |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVC2952ADW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC2952ADW | SN74LVC2952ADW |
| SN74LVC2952ADWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC2952ADWE4 | SN74LVC2952ADWE4 |
| SN74LVC2952ADWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC2952ADWG4 | SN74LVC2952ADWG4 |
