ADS62P48 具有 DDR LVDS 和并行 CMOS 输出的双通道 14 位、210MSPS ADC
The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.
|
ADS6128 |
ADS6129 |
ADS6148 |
ADS6149 |
ADS61B29 |
ADS61B49 |
ADS62P28 |
ADS62P29 |
ADS62P48 |
ADS62P49 |
| Resolution(Bits) |
12 |
12 |
14 |
14 |
12 |
14 |
12 |
12 |
14 |
14 |
| Sample Rate (max) |
210MSPS |
250MSPS |
210MSPS |
250MSPS |
250MSPS |
250MSPS |
210MSPS |
250MSPS |
210MSPS |
250MSPS |
| Architecture |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
| Power Consumption(Typ)(mW) |
628 |
687 |
628 |
687 |
790 |
790 |
1140 |
1250 |
1140 |
1250 |
| SINAD(dB) |
70.4 |
70.4 |
72.4 |
72.4 |
69.7 |
71.8 |
70.5 |
70.3 |
72.8 |
72.7 |
| SNR(dB) |
70.5 |
70.5 |
72.7 |
72.7 |
70 |
72.4 |
70.6 |
70.5 |
73 |
73 |
| SFDR(dB) |
82 |
86 |
82 |
86 |
86 |
86 |
85 |
85 |
85 |
85 |
| DNL(Max)(+/-LSB) |
1 |
1 |
2 |
2 |
1 |
1 |
|
|
1.3 |
1.3 |
| INL(Max)(+/-LSB) |
2.5 |
2.5 |
5 |
5 |
2.5 |
5 |
|
|
5 |
5 |
| No Missing Codes(Bits) |
12 |
12 |
14 |
14 |
12 |
14 |
12 |
12 |
14 |
14 |
| ENOB(Bits) |
11.40 |
11.4 |
11.73 |
11.73 |
11.28 |
11.63 |
11 |
11.1 |
11.4 |
11.3 |
| No. of Supplies |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| Analog Voltage AV/DD(Min)(V) |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.15 |
3.15 |
3.15 |
3.15 |
| Analog Voltage AV/DD(Max)(V) |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
| Logic Voltage DV/DD(Min)(V) |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
| Logic Voltage DV/DD(Max)(V) |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
| Input Configuration Range |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
| Reference Mode |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
| Rating |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
| Pin/Package |
48VQFN |
48VQFN |
48VQFN |
48VQFN |
48VQFN |
48VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
| # Input Channels |
1 |
1 |
1 |
1 |
1 |
1 |
2 |
2 |
2 |
2 |
| Operating Temp Range(Celsius) |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
ADS62P48 特性
- Maximum Sample Rate: 250 MSPS
- 14-Bit Resolution—ADS62P49/ADS62P48
- 12-Bit Resolution—ADS62P29/ADS62P28
- Total Power: 1.25 W at 250 MSPS
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- 90dB Cross-Talk
- Supports Input Clock Amplitude Down to 400 mVPP Differential
- Internal and External Reference Support
- 64-QFN Package (9 mm × 9 mm)
ADS62P48 芯片订购指南
ADS62P42 工具与软件
| 名称 |
型号 |
公司 |
工具/软件类型 |
| ADS62P28 评估模块 |
ADS62P28EVM |
Texas Instruments |
开发电路板/EVM |
| ADS62P48 评估模块 |
ADS62P48EVM |
Texas Instruments |
开发电路板/EVM |
| ADS62P49 评估模块 |
ADS62P49EVM |
Texas Instruments |
开发电路板/EVM |
| ADC 谐波计算器 |
ADC-HARMONIC-CALC |
Texas Instruments |
计算实用程序 |
| 用于模数转换器的抗混淆计算工具 |
ANTIALIASINGCALC |
Texas Instruments |
计算实用程序 |
| 运算放大器至 ADC 电路拓扑计算器 |
ADC-INPUT-CALC |
Texas Instruments |
计算实用程序 |
ADS62P42 质量与无铅数据
ADS62P48 应用技术支持与电子电路设计开发资源下载
- ADS62P48 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- A
Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF
461 KB)
- A Spreadsheet for Calculating the Frequency Response of the
ADS1250-54
- Understanding the ADS1251, ADS1253, and ADS1254 Input
Circuitry (PDF 39 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)
