CD40117B 可编程双路 4 位终端 (20V 额定)

CD40117B is a dual 4-bit terminator that can be programmed by means of STROBE and DATA control bits to function as pull-up or pull-down resistors. The CD40117B can also be programmed to function as latches to terminate any open or unused CMOS logic when used with 3-state logic or during a power-down condition. Considerable savings in power and board space can be realized when this device is used to replace pull-up or pull-down resistors. When the STROBE is in the logic "1" state, the terminator functions as a pull-up resistor if the DATA input is a logic "1" or as a pull down resistor if the DATA input is a logic "0".

When the STROBE is in the logic "0" state, the terminator performs the latch functions,

CD40117B
Voltage Nodes(V) 5, 10, 15  
Technology Family CD4000
CD40117B 特性
CD40117B 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD40117BE ACTIVE -55 to 125 1.15 | 1ku PDIP (N) | 14 25 | TUBE  
CD40117BEE4 ACTIVE -55 to 125 1.15 | 1ku PDIP (N) | 14 25 | TUBE  
CD40117BMT ACTIVE -55 to 125 1.55 | 1ku SOIC (D) | 14 250 | SMALL T&R  
CD40117BMTE4 ACTIVE -55 to 125 1.55 | 1ku SOIC (D) | 14 250 | SMALL T&R  
CD40117BMTG4 ACTIVE -55 to 125 1.55 | 1ku SOIC (D) | 14 250 | SMALL T&R  
CD40117B 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD40117BE Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD40117BE CD40117BE
CD40117BEE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD40117BEE4 CD40117BEE4
CD40117BMT Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD40117BMT CD40117BMT
CD40117BMTE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD40117BMTE4 CD40117BMTE4
CD40117BMTG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD40117BMTG4 CD40117BMTG4
CD40117B 应用技术支持与电子电路设计开发资源下载
  1. CD40117B 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)