TLC3578IPW 串行输出、低功耗，具有内置转换时钟 8x FIFO、8 通道TSSOP-24封装
|
TLC3578 |
| Resolution(Bits) |
14 |
| Sample Rate (max) |
200kSPS |
| Architecture |
SAR |
| Power Consumption(Typ)(mW) |
29 |
| SINAD(dB) |
79 |
| SNR(dB) |
80 |
| SFDR(dB) |
83 |
| DNL(Max)(+/-LSB) |
1 |
| INL(Max)(+/-LSB) |
1.5 |
| No Missing Codes(Bits) |
14 |
| ENOB(Bits) |
12.83 |
| No. of Supplies |
2 |
| Analog Voltage AV/DD(Min)(V) |
4.5 |
| Analog Voltage AV/DD(Max)(V) |
5.5 |
| Logic Voltage DV/DD(Min)(V) |
2.7 |
| Logic Voltage DV/DD(Max)(V) |
5.5 |
| Input Configuration Range |
+/-10V |
| Reference Mode |
Ext |
| Rating |
Catalog |
| Pin/Package |
24SOIC, 24TSSOP |
| # Input Channels |
8 |
| Operating Temp Range(Celsius) |
-40 to 85 |
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter.
TLC3578IPW 特性
- 14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
- Maximum Throughput 200-KSPS
- Multiple Analog Inputs:
- 8 Single-Ended Channels for TLC3578/2578
- 4 Single-Ended Channels for TLC3574/2574
- Analog Input Range: ±10 V
- Pseudodifferential Analog Inputs
- SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
- Built-In Conversion Clock and 8x FIFO
- Single 5-V Analog Supply; 3-/5-V Digital Supply
- Low-Power
- 5.8 mA in Normal Operation
- 20 µA in Power Down
- Programmable Autochannel Sweep and Repeat
- Hardware-Controlled, Programmable Sampling Period
- Hardware Default Configuration
- INL: TLC3574/78: ±1 LSB;
TLC2574/78: ±0.5 LSB
- DNL: TLC3574/78: ±0.5 LSB;
TLC2574/78: ±0.5 LSB
- SINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
- THD: TLC3574/78: –82 dB;
TLC2574/78: –82 dB
TLC3578IPW 芯片订购指南
TLC3578IPW 应用技术支持与电子电路设计开发资源下载
- TLC3578IPW 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
