TS3A5017 14Ω 双 SP4T 模拟开关 3.3 伏/2.5 伏模拟多路复用器/多路解复用器

The TS3A5017 is a dual single-pole quadruple-throw (4:1) analog switch that is designed to operate from 2.3 V to 3.6 V. This device can handle both digital and analog signals, and signals up to V+ can be transmitted in either direction.

TS3A5017
Configuration 2 X SP4T  
ron(max)(ohms) 12  
IL OFF(Max)(nA) 5000  
OFF Time(Max)(ns) 4.5  
ON Time(Max)(ns) 10.5  
Operating Temperature Range(°C) -40 to 85  
Pin/Package 16SOIC
Approx. Price (US$) 0.43 | 1ku  
VCC(Min)(V) 3.6  
tpd max(ns) 9.5  
Voltage Nodes(V) 2.5, 3.0, 3.3  
RON Flatness(Max)(Ohms) 9  
Technology Family TS  
ESD Rating(kV) 2kV HBM  
Bandwidth(MHz) 165  
Charge Injection(Max)(pC) 5  
RON Mis-match(Max)(Ohms) 2  
Voltage Node(V) 2.5, 3.0, 3.3  
Vcc max(V) 3.6  
Vcc min(V) 2.3  
Number of Channels 4  
ICC(uA) 10  
Rating Catalog
TS3A5017 特性
TS3A5017 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
TS3A5017D ACTIVE -40 to 85 0.55 | 1ku SOIC (D) | 16 40 | TUBE  
TS3A5017DE4 ACTIVE -40 to 85 0.55 | 1ku SOIC (D) | 16 40 | TUBE  
TS3A5017DG4 ACTIVE -40 to 85 0.55 | 1ku SOIC (D) | 16 40 | TUBE  
TS3A5017DR ACTIVE -40 to 85 0.43 | 1ku SOIC (D) | 16 2500 | LARGE T&R  
TS3A5017DRE4 ACTIVE -40 to 85 0.43 | 1ku SOIC (D) | 16 2500 | LARGE T&R  
TS3A5017DRG4 ACTIVE -40 to 85 0.43 | 1ku SOIC (D) | 16 2500 | LARGE T&R  
TS3A5017 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
TS3A5017D Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017D TS3A5017D
TS3A5017DE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017DE4 TS3A5017DE4
TS3A5017DG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017DG4 TS3A5017DG4
TS3A5017DR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017DR TS3A5017DR
TS3A5017DRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017DRE4 TS3A5017DRE4
TS3A5017DRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM TS3A5017DRG4 TS3A5017DRG4
TS3A5017 应用技术支持与电子电路设计开发资源下载
  1. TS3A5017 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器信号开关产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)