GaN FET 模块

Part Number Status Configuration Driver Configuration RDS(on) Typ at Iout 5A(milliohm) Vin SW (max)(Max)(V) ID Max at TC 25degC(Max)(A) Prop Delay(ns) Prop Delay Matching(ns) PulseWidth Min(ns) Logic Level UVLO Thresholds On/Off(V) VCC(V) Control Method Drivers(Count)
LMG5200 ACTIVE Half Bridge Power Stage High Side and Low Side 14 80 10 29 2 10 3V to 5V CMOS and TTL 3.8 5 External 2