AD6623AS: 104 MSPS, Four-Channel Digital Transmit Signal Processor (TSP)
The AD6623 is a four channel Transmit Signal Processor (TSP) that creates high bandwidth data for Transmit Digital-to-Analog Converters (TxDAC®s) from baseband data provided by a Digital Signal Processor (DSP). Modern TxDACs have achieved sufficiently high sampling rates, analog bandwidth, and dynamic range to create the first Intermediate Frequency (IF) directly. The AD6623 synthesizes multi-carrier and multi-standard digital signals to drive these TxDACs. The RAM-based architecture allows easy reconfiguration for multi-mode applications. Modulation, pulse-shaping and anti-imaging filters, static equalization, and tuning functions are combined in a single, cost-effective device. Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high dynamic range analog designs.
The AD6623 is pin compatible to the AD6622 and can operate in AD6622 compatible control register mode.
Each TSP has five cascaded signal processing elements: a programmable interpolating RAM Coefficient Filter (RCF), a programmable Scale and Power Ramp, a programmable 5th order Cascaded Integrator Comb (CIC5) interpolating filter, a flexible 2nd order Re-Sampling Cascaded Integrator Comb filter (rCIC2), and a Numerically Controlled Oscillator/tuner (NCO). The AD6623 has four identical digital TSPs complete with synchronization circuitry and cascadable wideband channel summation. The outputs of the four TSPs are summed and scaled on-chip. In multi-carrier channel wideband transmitters, a bi-directional bus allows the Parallel (wideband) IF Input/Output to drive a second DAC. In this operational mode two AD6623 channels drive one DAC and the other two AD6623 channels drive a second DAC. Multiple AD6623s may be combined by driving the INOUT[17:0] of the succeeding with the OUT[17:0] of the preceding chip. The INOUT[17:0] can alternatively be masked off by software to allow preceding AD6623s outputs to be ignored.
Each channel accepts input data from independent serial ports that may be connected directly to the serial port of Digital Signal Processor (DSP) chips. The AD6623 utilizes a 3.3V I/O power supply and a 2.5V core power supply. All I/O pins are 5V tolerant. All control registers and coefficient values are programmed through a generic microprocessor interface. Intel and Motorola microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible.
AD6623AS 特点
- RAM Coefficient Filter (RCF) Programmable IF And Modulation For Each Channel Programmable Interpolating RAM Coefficient Filter p/4 DQPSK Differential Phase Encoder 3p/8 8-PSK Linear Encoder 8-PSK Linear Encoder
- Programmable GMSK Look-Up Table Programmable QPSK Look-Up-Table All-Pass Phase Equalizer Programmable Fine Scalar Programmable Power Ramp Unit
- 18-Bit Parallel Digital IF Output
- 18-Bit Bi-Directional Parallel Digital IF Input/Output Allows Cascade Of Chips For Additional Channels
- Four Independent Digital Transmitters In Single Package
- Digital Re-Sampling For Non-Integer Decimation Rates
AD6623AS 功能框图
| 产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
|---|---|---|---|---|
| AD6623ABC | 量产 | 196 ball CSPBGA (1.70mm thick) | 196 | Ind |
| AD6623ABCZ | 量产 | 196 ball CSPBGA (1.70mm thick) | 196 | Ind |
| AD6623AS | 量产 | 128 ld MQFP (14x20mm) | 128 | Ind |
| AD6623ASZ | 量产 | 128 ld MQFP (14x20mm) | 128 | Ind |
