XRT71D00 Single-Chip Jitter Attenuator for DS3/E3/STS-1 WANs

Exar's XRT71D00 jitter attenuator circuit provides a fresh approach which promises to match, or outperform other methods, and is considerably easier to deploy at a lower cost. The XRT71D00 meets the European elecommunication Standards Institute (ETSI), technical committee draft standards TBR24 (34.368 Mbits/sec digital unstructured and structured leased lines. Both TBR24, and Bellcore GR-499 require that terminal equipment, which derives its timing from the received signal at the input port, must not exceed specified output jitter levels. The XRT71D00 performs the jitter attenuation for both E3 (34.368 Mbits/sec) and DS3 (44.736 Mbits/sec)rates enabling development of full standards compliant E3/DS3 products.

技术特性

Accepts "jittery" clock and data from an LIU IC
Internally reduces clock and data signal jitter
Outputs "smooth" data to the terminal equipment
Selectable buffer size of 16- and 32-bits
Jitter attenuator can be disabled
Available in 24-pin SOIC, or 32-pin TQFP package
Single 3.3V, or 5.0V supply
Pb-Free, RoHS Compliant Versions Offered

订购信息 Ordering Information

器件型号	有害物质限制	最低温度	最高温度	状态	立刻购买	申请样片
XRT71D00IQ-F		-40	85	Active

技术指标

频道数量	1
数据传输速率(s)	DS3, E3, STS-1
Clk Rec	No
短途/长途	n/a
温度.范围	Ind.
OpPwr Sup/Max Cur	3V, 5V, ±5%
封装	TQFP-32
Recommended

应用领域 APPLICATION

ETSI TBR-24 34Mbits/s D34U, and D34S systems
DS3/E3 Digital multiplex and de-multiplex equipment
DSLAM
ATM equipment
PCM Test equipment
E3/DS3 Access equipment

应用技术支持与电子电路设计开发资源下载	版本信息	大小
XRT71D00 数据资料DataSheet下载:pdf	Rev.V2	2 页