技术特性

• Receiver:
  
  • On chip Clock and Data Recovery circuit for high input jitter tolerance
    
  • Meets E3/DS3/STS-1 Jitter Tolerance Requirements
    
  • Detects and Clears LOS as per G.775
    
  • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation
    
  • On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled
    
  • On-chip Clock Synthesizer generates the appropriate rate clock from a single frequency Crystal
    
  • Provides low jitter clock outputs for either E3, DS3 or STS-1 rates in ITU-T G.823_1993 for E3
    
  • Pb-Free, RoHS Compliant Versions Offered

订购信息 Ordering Information

技术指标

应用领域 APPLICATION

• E3/DS3 Access Equipment
  
• STS1-SPE to DS3 Mapper
  
• DSLAMs
  
• Digital Cross Connect Systems
  
• CSU/DSU Equipment
  
• Routers
  
• Fiber Optic Terminals

功能框图 Functional Block Diagram