MC100EP196:3.3 V ECL Programmable Delay Chip
The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps.
技术特性
- Maximum Frequency > 1.2 GHz Typical
- PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
- Open Input Default State
- Safety Clamp on Inputs
- A Logic High on the ENbar Pin Will Force Q to Logic Low
- D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
- VBB Output Reference Voltage
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100EP196FAG |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tray JEDEC |
250 |
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| MC100EP196FAR2G |
Active |
|
3.3 V ECL Programmable Delay Chip |
LQFP-32 |
873A-02 |
2 |
Tape and Reel |
2000 |
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