MC100LVELT20:LVTTL/LVCMOS to Differential LVPECL Translator
The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at a premium.
技术特性
- 390 ps Typical Propagation Delay
- Maximum Input Clock Frequency > 0.8 GHz Typical
- Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
- PNP TTL Input for Minimal Loading
- Pb-Free Packages are Available
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封装图 MARKING DIAGRAM
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订购信息 Ordering Information
| 产品 |
状况 |
Compliance |
具体说明 |
封装 |
MSL* |
容器 |
预算价格 (1千个数量的单价） |
| 类型 |
外形 |
类型 |
数量 |
| MC100LVELT20DG |
Active |
|
LVTTL/LVCMOS to Differential LVPECL Translator |
SOIC-8 |
751-07 |
1 |
Tube |
98 |
|
| MC100LVELT20DR2G |
Active |
|
LVTTL/LVCMOS to Differential LVPECL Translator |
SOIC-8 |
751-07 |
1 |
Tape and Reel |
2500 |
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数据资料DataSheet下载
