ADS6425 Low power monolithic 4-channel, 12-bit 125MSPS ADC
The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
ADS6422
ADS6423
ADS6424
ADS6425
ADS6442
ADS6443
ADS6444
ADS6445
Resolution(Bits)
12
12
12
12
14
14
14
14
Sample Rate (max)
65MSPS
80MSPS
105MSPS
125MSPS
65MSPS
80MSPS
105MSPS
125MSPS
Architecture
Pipeline
Pipeline
Pipeline
Pipeline
Pipeline
Pipeline
Pipeline
Pipeline
Power Consumption(Typ)(mW)
1050
1180
1350
1650
1050
1180
1350
1680
SINAD(dB)
71
70.9
70
70
73.7
73.5
72
72.3
SNR(dB)
71
70.9
70.6
70.5
74
73.8
73
73.2
SFDR(dB)
88
87
81
83
88
87.5
81
83
DNL(Max)(+/-LSB)
0.5
1.8
2
2
0.5
2
2.5
2.5
INL(Max)(+/-LSB)
2
2
2.5
2.5
4.5
4.5
5
5
No Missing Codes(Bits)
12
12
12
12
14
14
14
14
ENOB(Bits)
11.5
11.5
11.4
11.4
12
11.9
11.7
11.7
No. of Supplies
2
2
2
2
2
2
2
2
Analog Voltage AV/DD(Min)(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Analog Voltage AV/DD(Max)(V)
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
Logic Voltage DV/DD(Min)(V)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
Logic Voltage DV/DD(Max)(V)
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.3
Input Configuration Range
2V (p-p)
2V (p-p)
2V (p-p)
2V (p-p)
2V (p-p)
2V (p-p)
2V (p-p)
2V (p-p)
Reference Mode
Int and Ext
Int and Ext
Int and Ext
Int and Ext
Int and Ext
Int and Ext
Int and Ext
Int and Ext
Rating
Catalog
Catalog
Catalog
Catalog
Catalog
Catalog
Catalog
Catalog
Pin/Package
64VQFN
64VQFN
64VQFN
64VQFN
64VQFN
64VQFN
64VQFN
64VQFN
# Input Channels
4
4
4
4
4
4
4
4
Operating Temperature Range(°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS6425 特性
Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
1.65-W Total Power
Simultaneous Sample and Hold
70.3 dBFS SNR at Fin = 50 MHz
83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
Serialized LVDS Outputs with Programmable Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
Internal Reference with External Reference Support
No External Decoupling Required for References
3.3-V Analog and Digital Supply
64 QFN Package (9 mm × 9 mm)
Pin Compatible 14-Bit Family (ADS644X - SLAS532)
APPLICATIONS
Base-Station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
ADS6425 芯片订购指南
ADS6425 工具与软件
名称
型号
公司
工具/软件类型
ADS6425 评估模块
ADS6425EVM
Texas Instruments
开发电路板/EVM
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ADC-HARMONIC-CALC
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ANTIALIASINGCALC
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ADC-INPUT-CALC
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ADS6425 质量与无铅数据
ADS6425 应用技术支持与电子电路设计开发资源下载
ADS6425 数据资料 dataSheet 下载 .PDF
TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
所选封装材料的热学和电学性质 (PDF 645 KB)
高速数据转换 (PDF 1967 KB) Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
A
Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF
461 KB)
A Spreadsheet for Calculating the Frequency Response of the
ADS1250-54
Understanding the ADS1251, ADS1253, and ADS1254 Input
Circuitry (PDF 39 KB)
Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
Principles of Data Acquisition and Conversion (PDF 50 KB)
Interleaving Analog-to-Digital Converters (PDF 64 KB)
What
Designers Should Know About Data Converter Drift (PDF 95 KB)
Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)