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LTC3831-1 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination

The LTC®3831-1 is a high power, high efficiency switching regulator controller designed for DDR memory termination. The LTC3831-1 generates an output voltage equal to 1/2 of an external supply or reference voltage. The LTC3831-1 uses a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel FET, providing an adjustable current limit without a current sense resistor.

The LTC3831-1 operates with input supply voltage as low as 3V and with a maximum duty cycle of >91%. It includes a fixed frequency PWM oscillator for low output ripple operation. The 300kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to above 500kHz. In shutdown mode, the LTC3831-1 supply current drops to <10µA.

特点 VOUT as Low as 0.4V High Power Switching Regulator Controller for DDR Memory Termination VOUT Tracks 1/2 of VIN or External VREF No Current Sense Resistor Required Low VCC Supply: 3V to 8V Maximum Duty Cycle > 91% Over Temperature Drives All N-Channel External MOSFETs High Efficiency: Up to 95% Programmable Fixed Frequency Operation:100kHz to 500kHz External Clock Synchronization Operation Programmable Soft-Start Low Shutdown Current: <10µA Overtemperature Protection Available in 16-Pin Narrow SSOP Package 典型应用

应用 DDR SDRAM Termination SSTL_2, SSTL_3 Interface HSTL Interface 封装信息