产品特性

• Optimized for the highest performance applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 32-bit and 16-bit embedded CPU’s
• Integrated PHY with HP Auto-MDIX Support
• Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams
• Compatible with other members of LAN9218 family
• Video distribution systems, multi-room PVR
• Cable, satellite, and IP set-top boxes
• Digital video recorders and DVD recorder/players
• Digital TV
• Digital media clients/servers and home gateways
• Video-over IP Solutions, IP PBX & video phones
• Wireless routers & access points
• High-end audio distribution systems
• Non-PCI Ethernet controller for the highest performance applications Highest performing non-PCI Ethernet controller 32-bit interface with fast bus cycle times Burst-mode read support
• Highest performing non-PCI Ethernet controller
• 32-bit interface with fast bus cycle times
• Burst-mode read support
• Eliminates dropped packets Internal buffer memory can store over 200 packets Automatic PAUSE and back-pressure flow control
• Internal buffer memory can store over 200 packets
• Automatic PAUSE and back-pressure flow control
• Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer
• Supports Slave-DMA
• Interrupt Pin with Programmable Hold-off timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
• Reduced-Power Modes Numerous power management modes Wake on LAN* Magic packet wakeup* Wakeup indicator event signal Link Status Change
• Numerous power management modes
• Wake on LAN*
• Magic packet wakeup*
• Wakeup indicator event signal
• Link Status Change
• Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes
• Fully compliant with IEEE 802.3/802.3u standards
• Integrated Ethernet MAC and PHY
• 10BASE-T and 100BASE-TX support
• Full- and Half-duplex support
• Full-duplex flow control
• Backpressure for half-duplex flow control
• Preamble generation and removal
• Automatic 32-bit CRC generation and checking
• Automatic payload padding and pad removal
• Loop-back modes
• Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets
• One 48-bit perfect address
• 64 hash-filtered multicast addresses
• Pass all multicast
• Promiscuous mode
• Inverse filtering
• Pass all incoming with status report
• Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY Supports HP Auto-MDIX Auto-negotiation Supports energy-detect power down
• Supports HP Auto-MDIX
• Auto-negotiation
• Supports energy-detect power down
• Host bus interface Simple, SRAM-like interface 32 or 16-bit data bus 16Kbyte FIFO with flexible TX/RX allocation One configurable host interrupt
• Simple, SRAM-like interface
• 32 or 16-bit data bus
• 16Kbyte FIFO with flexible TX/RX allocation
• One configurable host interrupt
• Miscellaneous features Low-profile 100-pin TQFP, RoHS Compliant package Integrated 1.8V regulator General Purpose Timer Optional EEPROM interface Support for 3 status LEDs multiplexed with Programmable GPIO signals
• Low-profile 100-pin TQFP, RoHS Compliant package
• Integrated 1.8V regulator
• General Purpose Timer
• Optional EEPROM interface
• Support for 3 status LEDs multiplexed with Programmable GPIO signals
• Single 3.3V Power Supply with 5V tolerant I/O
• Commercial and Industrial (LAN9218i) Temperature Support

技术参数