67bit LVDS Receiver - BU90R102

The BU90R102 receiver operates from 8MHz to 160MHz wide clock range. The BU90R102 converts the 10Lane (2Channel) LVDS serial data streams back into 67bit of LVCMOS parallel data. Data is transmitted seven times (7X) stream and reduce the cable number by 3 (1/3) or less. I/O Voltage range is 2.3 to 3.6V, so it is available for many products. Flexible Input/Output mode is suitable for a variety of application Interface.

Part NumberStatusPackageUnit QuantityMinimum Package QuantityPacking TypeRoHS
BU90R102ActiveHQFP144VM6060TrayYes

BU90R102 Data Sheet

Specifications
Sub FamilyLVDS SerDes
FunctionDeserializer
Input Signal TypeLVDS
Output Signal TypeLVCMOS
No.of Rx10
Clock frequency (Min.)[MHz]8
Clock frequency (Max.)[MHz]160
Data Rates [Mbps]1120
Parallel Bus Width67
Supply Voltage(Min.)[V]2.3
Supply Voltage(Max.)[V]3.6
Supply Voltage(Typ.)[V]3.3
Operating Temperature (Min.)[°C]-40
Operating Temperature (Max.)[°C]85
Technical Documents
Features
  • The maximum data rate is 1120Mbps/Lane
  • It enables to receive the 60bit of RGB data, 7bit of Timing and Control data
  • Support clock frequency from 8MHz up to 160MHz
  • Flexible Input/Output mode
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