ADS62P15 具有并行 CMOS/DDR LVDS 输出的双通道 11 位 125MSPS ADC
ADS62P15 同类产品
- CDCE72010 - Recommended clocking solution, providing low jitter clock outputs to maximize converter performance
ADS62P15 说明
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
|
ADS62P15 |
ADS62P22 |
ADS62P23 |
ADS62P24 |
ADS62P25 |
ADS62P42 |
ADS62P43 |
ADS62P44 |
ADS62P45 |
| Resolution(Bits) |
11 |
12 |
12 |
12 |
12 |
14 |
14 |
14 |
14 |
| Sample Rate (max) |
125MSPS |
65MSPS |
80MSPS |
105MSPS |
125MSPS |
65MSPS |
80MSPS |
105MSPS |
125MSPS |
| Architecture |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
| Power Consumption(Typ)(mW) |
740 |
518 |
587 |
700 |
792 |
518 |
587 |
700 |
792 |
| SINAD(dB) |
66.9 |
70.8 |
70.8 |
70.2 |
70.2 |
73.7 |
73.6 |
73.4 |
73.2 |
| SNR(dB) |
67.1 |
71.3 |
71.2 |
70.8 |
70.8 |
74.3 |
74.2 |
73.8 |
73.8 |
| SFDR(dB) |
84 |
88 |
88 |
86 |
85 |
88 |
88 |
86 |
85 |
| DNL(Max)(+/-LSB) |
0.8 |
0.4 |
0.5 |
0.7 |
0.8 |
0.4 |
0.5 |
0.7 |
0.8 |
| INL(Max)(+/-LSB) |
3.5 |
1.5 |
1.5 |
2.5 |
3 |
1.5 |
1.5 |
2.5 |
3 |
| No Missing Codes(Bits) |
11 |
12 |
12 |
12 |
12 |
14 |
14 |
14 |
14 |
| ENOB(Bits) |
10.8 |
11.4 |
11.4 |
11.4 |
11.4 |
12 |
11.9 |
11.8 |
11.8 |
| No. of Supplies |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| Analog Voltage AV/DD(Min)(V) |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
| Analog Voltage AV/DD(Max)(V) |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
| Logic Voltage DV/DD(Min)(V) |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
| Logic Voltage DV/DD(Max)(V) |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
| Input Configuration Range |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
| Reference Mode |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
| Rating |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
| Pin/Package |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
| # Input Channels |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
| Operating Temp Range(Celsius) |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
ADS62P15 特性
- Maximum Sample Rate: 125 MSPS
- 11-Bit Resolution With No Missing Codes
- 84 dBc SFDR at Fin = 50 MHz
- 67.1 dBFS SNR at Fin = 50 MHz
- 92 dB Crosstalk
- Parallel CMOS and DDR LVDS Output Options
- 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off
- Digital Processing Block With:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low/High /Band Pass Filters
- Supports Sine, LVPECL, LVDS & LVCMOS Clocks & Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference; Supports External Reference also
- 64-QFN Package (9mm × 9mm)
- Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X)
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
ADS62P15 芯片订购指南
| 器件 |
状态 |
温度 (oC) |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| ADS62P15IRGC25 |
ACTIVE |
-40 to 85 |
29.10 | 100u |
VQFN (RGC) | 64 |
25 | SMALL T&R |
AZ62P15 |
| ADS62P15IRGCR |
ACTIVE |
-40 to 85 |
22.50 | 100u |
VQFN (RGC) | 64 |
2000 | LARGE T&R |
AZ62P15 |
| ADS62P15IRGCRG4 |
ACTIVE |
-40 to 85 |
22.50 | 100u |
VQFN (RGC) | 64 |
2000 | LARGE T&R |
AZ62P15 |
| ADS62P15IRGCT |
ACTIVE |
-40 to 85 |
23.80 | 100u |
VQFN (RGC) | 64 |
250 | SMALL T&R |
AZ62P15 |
| ADS62P15IRGCTG4 |
ACTIVE |
-40 to 85 |
23.80 | 100u |
VQFN (RGC) | 64 |
250 | SMALL T&R |
AZ62P15 |
ADS62P15 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| ADS62P15IRGC25 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
|
ADS62P15IRGC25 |
| ADS62P15IRGCR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
|
ADS62P15IRGCR |
| ADS62P15IRGCRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
ADS62P15IRGCRG4 |
ADS62P15IRGCRG4 |
| ADS62P15IRGCT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
|
ADS62P15IRGCT |
| ADS62P15IRGCTG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
ADS62P15IRGCTG4 |
ADS62P15IRGCTG4 |
ADS62P15 应用技术支持与电子电路设计开发资源下载
- ADS62P15 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- A
Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF
461 KB)
- A Spreadsheet for Calculating the Frequency Response of the
ADS1250-54
- Understanding the ADS1251, ADS1253, and ADS1254 Input
Circuitry (PDF 39 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)
ADS62P15 工具与软件
