ADS62P44 具有可选 DDR LVDS 或 CMOS 输出的双路 14 位 105MSPS ADC
ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
|
ADS62P15 |
ADS62P22 |
ADS62P23 |
ADS62P24 |
ADS62P25 |
ADS62P42 |
ADS62P43 |
ADS62P44 |
ADS62P45 |
Resolution(Bits) |
11 |
12 |
12 |
12 |
12 |
14 |
14 |
14 |
14 |
Sample Rate (max) |
125MSPS |
65MSPS |
80MSPS |
105MSPS |
125MSPS |
65MSPS |
80MSPS |
105MSPS |
125MSPS |
Architecture |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Pipeline |
Power Consumption(Typ)(mW) |
740 |
518 |
587 |
700 |
792 |
518 |
587 |
700 |
792 |
SINAD(dB) |
66.9 |
70.8 |
70.8 |
70.2 |
70.2 |
73.7 |
73.6 |
73.4 |
73.2 |
SNR(dB) |
67.1 |
71.3 |
71.2 |
70.8 |
70.8 |
74.3 |
74.2 |
73.8 |
73.8 |
SFDR(dB) |
84 |
88 |
88 |
86 |
85 |
88 |
88 |
86 |
85 |
DNL(Max)(+/-LSB) |
0.8 |
0.4 |
0.5 |
0.7 |
0.8 |
0.4 |
0.5 |
0.7 |
0.8 |
INL(Max)(+/-LSB) |
3.5 |
1.5 |
1.5 |
2.5 |
3 |
1.5 |
1.5 |
2.5 |
3 |
No Missing Codes(Bits) |
11 |
12 |
12 |
12 |
12 |
14 |
14 |
14 |
14 |
ENOB(Bits) |
10.8 |
11.4 |
11.4 |
11.4 |
11.4 |
12 |
11.9 |
11.8 |
11.8 |
No. of Supplies |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
Analog Voltage AV/DD(Min)(V) |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
Analog Voltage AV/DD(Max)(V) |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
Logic Voltage DV/DD(Min)(V) |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
3.0 |
Logic Voltage DV/DD(Max)(V) |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
3.6 |
Input Configuration Range |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
2V (p-p) |
Reference Mode |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Int and Ext |
Rating |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Pin/Package |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
64VQFN |
# Input Channels |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
2 |
Operating Temp Range(Celsius) |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
ADS62P44 特性
- Maximum Sample Rate: 125 MSPS
- 14-Bit Resolution with No Missing Codes
- 95 dB Crosstalk
- Parallel CMOS and DDR LVDS Output Options
- 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off
- Digital Processing Block with:
- Offset Correction
- Fine Gain Correction, in Steps of 0.05 dB
- Decimation by 2/4/8
- Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters
- Supports Sine, LVPECL, LVDS and LVCMOS Clocks and Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference; Supports External Reference also
- 64-QFN Package (9mm × 9mm)
- Pin Compatible 12-Bit Family (ADS62P2X)
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
ADS62P44 芯片订购指南
ADS62P44 工具与软件
名称 |
型号 |
公司 |
工具/软件类型 |
ADS62P24 评估模块 |
ADS62P24EVM |
Texas Instruments |
开发电路板/EVM |
ADS62P44 评估模块 |
ADS62P44EVM |
Texas Instruments |
开发电路板/EVM |
ADC 谐波计算器 |
ADC-HARMONIC-CALC |
Texas Instruments |
计算实用程序 |
用于模数转换器的抗混淆计算工具 |
ANTIALIASINGCALC |
Texas Instruments |
计算实用程序 |
运算放大器至 ADC 电路拓扑计算器 |
ADC-INPUT-CALC |
Texas Instruments |
计算实用程序 |
ADS62P44 质量与无铅数据
ADS62P44 应用技术支持与电子电路设计开发资源下载
- ADS62P44 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- A
Spreadsheet for Calculating the Frequency Response of the ADS1250-54 (PDF
461 KB)
- A Spreadsheet for Calculating the Frequency Response of the
ADS1250-54
- Understanding the ADS1251, ADS1253, and ADS1254 Input
Circuitry (PDF 39 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)