This document provides an overview of the space-grade, radiation-tolerant Virtex®-4QV family.

This data sheet provides the DC and switching characteristics for the space-grade, radiation-tolerant Virtex®-4QV FPGAs.

This data sheet provides electrical characteristics, packaging, and pinout information for the radiation-hardened QPro™ Virtex® 2.5V FPGAs.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain XC1700, XC4000E, XC4000XLA, XC5200, Spartan®-IIE, Spartan-3AN, Virtex®, Virtex-E, Virtex-II, CPLD and Aerospace & Defense “XQ” products.

To communicate that Xilinx is discontinuing certain Aerospace and Defense part numbers.

The purpose of this notification is to communicate that Xilinx is discontinuing certain XC3000, XC4000XL, XC5206, Virtex®, Spartan®-3 products, and Aerospace & Defense "XQ" products.

This notice describes the latest additions for obsolescence and should be considered in conjunction with previous discontinuance notices produced by Xilinx.

Xilinx will discontinue certain XQR2V6000 products with specific grades and package combinations due to supplier sustainability of an older product line with inconsistent run rate.

The purpose of this notice is to communicate changes in the assembly material set of the CF1144 package for the XQ2V6000-4CF1144M device. There is no change to the fit, form, function or reliability.

Xilinx 将停止生产某些低需求的军用及抗辐射产品。

Xilinx 将停止生产某些低需求的军用及抗辐射产品。

本通告传达了用于 V 级 QPro FPGA 器件的测试设备中的变动。

To inform Xilinx customers of the removal of Xilinx support for Parity Checking for PowerPC®405 in all Virtex®-4 FX FPGAs for the "XC" Commercial "C", Industrial "I", and Aerospace/Defense "XQ" devices.

To announce the conversion of substrate material from BT to ABF build-up for two Aerospace and Defense ‘XQ” Virtex&-II Pro FPGA device/packages.

To communicate a change in the wafer fabrication and sort facility for XQ18V04VQ44N flash memory configuration PROM device for Aerospace and Defense “XQ” products.

To announce that Xilinx is qualifying a new vendor for the glass material that is used on the lid of the 44L Cerquad CC44 package.

用于 Xilinx® FPGA PowerPC® 系统的 Single-Event Upset 减轻辐射设计流程

设计文件:

• xapp1004.zip

本应用指南讨论了各个方面的 single-event upset 并为每种环境推荐了适当的减轻辐射机制。

This application note discusses self-hosting configuration management hardware setup for Xilinx® FPGAs for the purpose of detecting and correcting single-event upsets (SEUs) to the configuration memory array.

本应用指南描述了结合利用三重模块冗余 (TMR) 和用于在高辐射环境中清洗 Xilinx 专用 block RAM 的配置，来减轻 SEU 的技巧。 其中还包含演示这些减轻技巧的设计示例。

设计文件:

• xapp962.zip

The Virtex®-4 FPGA User Guide includes chapters on Clocking Resources, Digital Clock Manager (DCM), Phase-Matched Clock Dividers (PMCD), Block RAM and FIFO memory, Configurable Logic Blocks (CLBs), SelectIO™ resources, and SelectIO logic resources.

设计文件:

• ug070.zip