• 简体中文
• English

MAX5865：Ultra-Low-Power, High-Dynamic-Performance, 40Msps Analog Front End

The MAX5865 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is ±0.2° and amplitude matching is ±0.05dB. The ADCs feature 48.4dB SINAD and 70dBc spurious-free dynamic range (SFDR) at fIN = 5.5MHz and fCLK = 40MHz. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is ±0.15° and gain matching is ±0.05dB. The DACs also feature dual 10-bit resolution with 72dBc SFDR, and 57dB SNR at fOUT = 2.2MHz and fCLK = 40MHz. The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 75.6mW at fCLK = 40Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5865 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5865 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 8.5mA in idle mode and 1µA in shutdown mode. The MAX5865 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.

Key Features Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs Ultra-Low Power 75.6mW at fCLK = 40MHz (Transceiver Mode) 64mW at fCLK = 22MHz (Transceiver Mode) Low-Current Idle and Shutdown Modes Excellent Dynamic Performance 48.4dB SINAD at fIN = 5.5MHz (ADC) 70dB SFDR at fOUT = 2.2MHz (DAC) Excellent Gain/Phase Match ±0.2° Phase, ±0.05dB Gain at fIN = 5.5MHz (ADC) Internal/External Reference Option +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible) Multiplexed Parallel Digital Input/Output for ADCs/DACs Miniature 48-Pin Thin QFN Package (7mm x 7mm) Evaluation Kit Available (Order MAX5865EVKIT)

MAX5865: Functional Diagram Applications/Uses 3G Wireless Terminals Fixed/Mobile Broadband Wireless Modems Narrowband/Wideband CDMA Handsets PDAs

DataSheet

Parametrics

Design kits & evaluation modules

• MAX5863EVKIT
• MAX5864EVKIT
• MAX5865EVKIT

Related Products

• MAX5866：Ultra-Low-Power, High-Dynamic-Performance, 60Msps Analog Front End
• MAX5863：Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End
• MAX5864：Ultra-Low-Power, High-Dynamic-Performance, 22Msps Analog Front End

Ordering Information