Spartan-6 FPGA 器件技术资料

器件数据手册DataSheet 下载
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DS160:7 Series FPGA Overview v1.7 308 KB
DS162:Spartan-6 FPGA Data Sheet:DC and Switching Characteristics v2.4 1.86 MB
7 Series FPGA User Guides 用户手册
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UG381:Spartan-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

ver 1.4 3.23 MB
UG383:Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan®-6 FPGA block RAM capabilities.

ver 1.5 933 KB
UG384:Spartan-6 FPGA Configurable Logic Block User Guide

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

ver 1.1 4.27 MB
UG386:Spartan-6 FPGA GTP Transceivers User Guide

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

ver 2.2 7.22 MB
UG389:Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

ver 1.1 1.64 MB
UG389:Spartan-6 FPGA PCB Design and Pin Planning Guide。

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

ver 1.2 10.3 MB
UG396:Spartan-6 FPGA GTP Transceiver Signal Integrity Simulation Kit User Guide for Mentor Graphics HyperLynx

The Spartan®-6 FPGA GTP Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx provides a simulation environment for evaluating channel designs for Spartan-6 FPGA GTP transceivers. This document describes how to install the SIS kit and get started with simulations.

ver 1.0 4.05 MB
7 Series FPGA Errata
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EN113:Spartan-6 FPGA LX16 CES Errata。 Errata for Spartan®-6 LX16 CES FPGAs. ver 1.5 212 KB
EN115:Spartan-6 FPGA LX150 CES Errata。Errata for Spartan®-6 LX150 CES FPGAs. ver 1.5 169 KB
EN117:Spartan-6 FPGA LX45 CES Errata。Errata for Spartan®-6 LX45 CES FPGAs. ver 1.5 152 KB
EN118:Spartan-6 FPGA LX45T CES Errata。Errata for Spartan®-6 LX45T CES FPGAs. ver 1.5 238 KB
EN124:Spartan-6 FPGA LX150T CES Errata。 Errata for Spartan®-6 LX150T CES FPGAs. ver 1.3 197 KB
EN146:Spartan-6 FPGA LX4, LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9953 Errata
Errata for the Spartan®-6 FPGA LX4, LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9953 devices.
ver 1.3 241 KB
EN147:Spartan-6 FPGA LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9951 Errata
Errata for the Spartan®-6 FPGA LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9951 devices.
ver 1.3 221 KB
EN148:Spartan-6 FPGA LX and LXT Production Errata
Errata for the Spartan®-6 FPGA production devices.
ver 1.9 232 KB
EN168:Lower Power Spartan-6 FPGA LX Production Errata
Errata for the Lower Power Spartan®-6 FPGA LX production devices.
ver 1.1 145 KB
Spartan-6 FPGA Customer Notices 用户注意事项
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XCN10024:MCB Performance, JTAG Revision Code and Max ICCINTQ and ICCAUXQ and SSO Table Updates for Spartan-6 LX16 and LX45 FPGAs
The purpose of this notification is to inform Xilinx customers of a change to the Memory Controller Block (MCB) performance, an update to the JTAG ID Revision Code, a change to the maximum ICCINTQ and ICCAUXQ specifications, and an update to the CSG324 Bank 0/2 SSO limit recommendations for “XC” Commercial Spartan®-6 LX16 -2C and Spartan-6 LX45 -2C FPGA production devices.
ver 1.2 130 KB
XCN11012:Mask Change for all Spartan-6 FPGA Devices, Speed File Change for -3N Devices
To communicate a mask change for all production Spartan®-6 FPGA devices and a speed file change for all Spartan-6 –3N speed devices.
ver 1.0 150 KB
XCN09033:Humidity Indicator Card (HIC) Change
To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.
ver 1.0 67 KB
XCN11018:Spartan, Virtex and CoolRunner Series Wire Bond BGA Packaging Material Source Addition
To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.
ver 1.0 170 KB
Spartan-6 FPGA Application Notes 应用手册
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XAPP879:PLL Dynamic Reconfiguration
This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan®-6 FPGA Phase Locked Loop (PLL) through its Dynamic Reconfiguration Port (DRP).


ver 1.1 419 KB
XAPP492:Extending the Spartan-6 FPGA Connectivity TRD (PCIe-DMA-DDR3-GbE) to Support the Aurora 8B/10B Serial Protocol
This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.


ver 1.0 6.89 MB
XAPP1065:Spread-Spectrum Clock Generation in Spartan-6 FPGAs
This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed spread-spectrum generation without any logic or in a soft spread-spectrum solution using a state machine.


ver 1.0 1.23 MB
XAPP1064:Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s)
This application note discusses how to efficiently use the Spartan®-6 FPGA ISERDES and OSERDES primitives in conjunction with the input delay blocks and phase-detector circuitry.


ver 1.1 1.07 MB
Spartan-6 FPGA Package Specifications
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CPG196:Material Declaration Data Sheet (Chip-Scale BGA)
100% Material Declaration Data Sheet CPG196 for Spartan®-6 FPGAs
ver 1.2 98 KB
CSG324:Material Declaration Data Sheet
100% Material Declaration Data Sheet:CSG324
ver 1.1 56 KB
FT256/FTG256:Package Drawing (Fine-Pitch Thin BGA) ver 1.4 113 KB
FG900/FGG900:Package Drawing (Fine-Pitch BGA)。
Package Drawing.
ver 1.4 134 KB
FTG256:Material Declaration Data Sheet (Pb-free Fine Pitch BGA)
100% Material Declaration Data Sheet FTG256 Package for Spartan-6 FPGAs
ver 1.0 91 KB
CPG196:Package Drawing (Chip-Scale BGA)
196 Ball Chip-Scale BGA (CPG196) Package
ver 1.0 131 KB
FG676:Material Declaration Data Sheet
Material Declaration Data Sheet, FG676 Package for Spartan-6 FPGAs
ver 1.0 90 KB
FGG484:Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)
100% Material Declaration Data Sheet FGG484
ver 1.0 85 KB
CSG225:Material Declaration Data Sheet (Chip-Scale BGA) ver 1.1 139 KB
CSG324:Package Drawing (324 Ball Chip-Scale BGA) ver 1.0 123 KB
FG900/FGG900:Package Drawing (Fine-Pitch BGA) ver 1.3 71 KB
CSG225:Package Drawing (225 Ball Chip-Scale BGA) ver 1.0 123 KB
TQ144/TQG144:Package Drawing (TQFP) ver 1.2 147 KB
TQG144:Material Declaration Data Sheet (Pb-free TQFP) ver 1.2.1 80 KB
FG484/FGG484:封装示意图(精确栅距 (Fine Pitch) BGA) ver 1.0 84 KB
FT256:Material Declaration Data Sheet (Standard Fine-Pitch Thin BGA) ver 1.3 143 KB
FGG900:Material Declaration Data Sheet (Pb-free Fine-Pitch BGA) ver 1.3 62 KB
FG484:Material Declaration Data Sheet (Standard Fine-Pitch BGA) ver 1.0.2 25 KB
FGG676:Material Declaration Data Sheet (Pb-free fine pitch BGA)。
100% Material Declaration Data Sheet, FGG676 Package for Spartan-6 FPGAs.
ver 1.0 86 KB
Spartan-6 FPGA Characterization Reports
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RPT131:Spartan-6 FPGA GTP Transceiver Characterization Report PCI Express 1.1 (2.5 Gb/s) Electrical Standard
This characterization report compares the electrical performance of the Spartan®-6 FPGA GTP transceiver against the PCI Express® Revision 1.1 specifications published in the PCI Express Base Specification, Revision 1.1 and the PCI Express Card Electromechanical Specification, Revision 1.1. All testing for this report is based on a line rate of 2.5 Gb/s across voltage, temperature, and worst-case transceiver performance corners.
ver 1.0 2.97 MB
Spartan-6 FPGA White Papers
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WP298:Power Consumption at 40 and 45 nm。
At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.
ver 1.0 1.59 MB
WP309:Targeting and Retargeting Guide for Spartan-6 FPGAs。
This white paper discusses targeting guidelines and other considerations needed to achieve optimal designs with Spartan®-6 devices.
ver 1.1 633 KB
WP311:Improving Performance in Spartan-6 FPGA Designs。
This white paper discusses how synthesis and implementation can help to optimize the performance of Spartan®-6 designs.
ver 1.2 252 KB
WP359:Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted Reference Designs。
This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.
ver 01 418 KB
WP360:Xilinx FPGA Embedded Memory Advantages。
The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.
ver 1.0 443 KB
WP363:Spartan-6 FPGA Connectivity Targeted Reference Design Performance。
This white paper discusses the observed performance of the Spartan®-6 FPGA Connectivity targeted reference design. The design uses PCI Express®, Ethernet, and an integrated memory controller along with a packet DMA for moving data between system memory and the FPGA.
ver 1.0 638 KB
WP368:Unlock New Levels of Productivity for Your Design Using ISE Design Suite 12。
ISE® Design Suite v12 is the production-optimized tool suite for Virtex®-6 and Spartan®-6 FPGAs that delivers innovation in three critical areas of FPGA design: power reduction, productivity, and performance.
ver 1.0 509 KB
WP370:Reducing Switching Power with Intelligent Clock Gating 。
Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.
ver 1.3 395 KB
WP378:Xilinx FPGAs in Portable Ultrasound Systems。
This white paper describes how design engineers can take advantage of Virtex®-6, Spartan®-6, and 7 series FPGAs to handle the complexity of designing portable ultrasound systems and bring cutting-edge ultrasound technology to market quickly within cost and power constraints.
ver 1.0.1 1.31 MB
WP379:AXI4 Interconnect Paves the Way to Plug-and-Play IP。
The AXI4 specification represents a major evolutionary step in interconnect technology for on-chip system design. The value of the AXI4 interconnect has many facets, beginning with an immediate gain in productivity derived from a unified IP interconnect standard that supplants legacy and custom interconnect architectures. The three interconnect protocols developed for the AXI4 standard (AXI4, AXI4-Lite, and AXI4-Stream interfaces) provide the flexibility to optimize an FPGA design for performance, throughput, latency, or area.
ver 1.0 376 KB
WP396:High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design。
The purpose of this white paper is to describe how Spartan®-6 FPGAs address the needs of high-volume systems. The ability to connect efficiently and inexpensively to commodity memories, high-performance chip-to-chip interface capability, and innovative power down modes are just a few of the problems solved by high-performance, low-power, and low-cost Spartan-6 FPGAs.
ver 1.0 722 KB